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understanding opcodes hLeps CPUIDflags progy

All-in-one reversing related discussions
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evaluator
Posts: 1539
Joined: Tue Sep 18, 2001 2:00 pm

understanding opcodes hLeps CPUIDflags progy

Post by evaluator »

so, as I am adding "new" itnel opcodes to rosasm assembler, need some help in understanding; as manual is now (325462-sdm-vol-1-2abcd-3abcd.pdf) in one file, I suspect, some opcodes of "atom" cpu are not for core cpus.

Code: Select all

; ATOM pc only? >
;ENCLS
;ENCLV
;CLDEMOTE
;PTWRITE
;TPAUSE
;UMONITOR
;UMWAIT
;MOVDIR64B
;MOVDIRI

;SHA1MSG1
;SHA1MSG2
;SHA1NEXTE
;SHA1RNDS4
;SHA256MSG1
;SHA256MSG2
;SHA256RNDS2
;RDPID ? NOT yet in gcc assembler?

INVPCID
RDPKRU
WRPKRU


also, there are xeonphi instructions, are they in desktop cpus?
edit:
created little cpuid flags reporter :)
Attachments
CPUID_flags_INFO_progy.zip
(9.29 KiB) Downloaded 63 times
User avatar
Kayaker
Posts: 4179
Joined: Thu Oct 26, 2000 11:00 am

Post by Kayaker »

What kind of info are you looking for? Most seem to be Googleable. I patched a few of those opcodes into Ghidra and not only did it recognize them, it gives a nice little drop-down box letting you choose the further operands available (keep pressing Enter as you build the instruction). Also if you right click and select Instruction Info there's further input/output details. That might be useful in understanding how to use them.
Attachments
opcodes_Ghidra.jpg
User avatar
evaluator
Posts: 1539
Joined: Tue Sep 18, 2001 2:00 pm

Post by evaluator »

are suspect opcodes for desktop Cpus? While Kayaker is out for hlep, guess, ourselves should examine CPUID EAX=7;ECX=0 CASE where EBX can hold these bits:

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CPUID EAX=7;ECX=0
EBX :
Bit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE 
Bit 01: IA32_TSC_ADJUST MSR
Bit 02: SGX
Bit 03: BMI1. 
Bit 04: HLE. 
Bit 05: AVX2. 
Bit 06: FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1. 
Bit 07: SMEP
Bit 08: BMI2. 
Bit 09: Supports Enhanced REP MOVSB/STOSB if 1. 
Bit 10: INVPCID
Bit 11: RTM. 
Bit 12: RDT-M.
Bit 13: Deprecates FPU CS and FPU DS values if 1. 
Bit 14: MPX.
Bit 15: RDT-A.
Bit 16: AVX512F. 
Bit 17: AVX512DQ. 
Bit 18: RDSEED. 
Bit 19: ADX. 
Bit 20: SMAP.
Bit 21: AVX512_IFMA. 
Bit 22: Reserved. 
Bit 23: CLFLUSHOPT. 
Bit 24: CLWB. 
Bit 25: Intel Processor Trace. 
Bit 26: AVX512PF. (Intel® Xeon PhiTM only.) 
Bit 27: AVX512ER. (Intel® Xeon PhiTM only.) 
Bit 28: AVX512CD. 
Bit 29: SHA. supports Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) if 1. 
Bit 30: AVX512BW. 
Bit 31: AVX512VL.
a-and Core 8th has:

Code: Select all

CPUID EAX=7;ECX=0
EBX :
Bit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE 
Bit 01: IA32_TSC_ADJUST MSR
Bit 02: SGX
Bit 03: BMI1. 

Bit 05: AVX2. 

Bit 07: SMEP
Bit 08: BMI2. 
Bit 09: Supports Enhanced REP MOVSB/STOSB if 1. 
Bit 10: INVPCID


Bit 13: Deprecates FPU CS and FPU DS values if 1. 
Bit 14: MPX.



Bit 18: RDSEED. 
Bit 19: ADX. 
Bit 20: SMAP.

Bit 22: Reserved. 
Bit 23: CLFLUSHOPT. 

Bit 25: Intel Processor Trace. 
ECX is NULL, thus these are gone :)

Code: Select all

ECX:
Bit 00: PREFETCHWT1. (Intel® Xeon Phi™ only.)
Bit 01: AVX512_VBMI.
Bit 02: UMIP. Supports user-mode instruction prevention if 1.
Bit 03: PKU. Supports protection keys for user-mode pages if 1.
Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions).
Bit 05: WAITPKG.
Bit 06: AVX512_VBMI2.
Bit 07: CET_SS. Supports CET shadow stack features
Bit 08: GFNI.
Bit 09: VAES.
Bit 10: VPCLMULQDQ.
Bit 11: AVX512_VNNI.
Bit 12: AVX512_BITALG.
Bit 13: Reserved.
Bit 14: AVX512_VPOPCNTDQ. (Intel® Xeon Phi™ only.)
Bit 16 - 15: Reserved.
Bit 21 - 17: The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.
Bit 22: RDPID and IA32_TSC_AUX are available if 1.
Bit 24 - 23: Reserved.
Bit 25: CLDEMOTE. Supports cache line demote if 1.
Bit 26: Reserved.
Bit 27: MOVDIRI. Supports MOVDIRI if 1.
Bit 28: MOVDIR64B. Supports MOVDIR64B if 1.
Bit 29: Reserved.
Bit 30: SGX_LC. Supports SGX Launch Configuration if 1.
Bit 31: Reserved.
and EDX is??

Code: Select all

EDX:
Bit 02: AVX512_4VNNIW. (Intel® Xeon Phi™ only.)
Bit 03: AVX512_4FMAPS. (Intel® Xeon Phi™ only.)
Bit 04: Fast Short REP MOV
Bit 15: Hybrid. If 1, the processor is identified as a hybrid part.
Bit 20: CET_IBT.
Bit 26: Enumerates support for (IBRS)
Bit 27: Enumerates support for (STIBP).
Bit 28: Enumerates support for L1D_FLUSH.
Bit 29: Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
Bit 30: Enumerates support for the IA32_CORE_CAPABILITIES MSR.
Bit 31: Enumerates support for (SSBD).

Code: Select all

Bit 10: ??
Bit 13: ??
Bit 26: Enumerates support for (IBRS)
Bit 27: Enumerates support for (STIBP).
Bit 28: Enumerates support for L1D_FLUSH.
Bit 31: Enumerates support for (SSBD).
blabberer
Senior Member
Posts: 1535
Joined: Wed Dec 08, 2004 11:12 am

Post by blabberer »

Code: Select all

[B][color="#FF0000"][font=Arial Black][size=134][url=https://github.com/JFLarvoire/SysToolsLib/releases/download/1.18/SysTools.zip]SysTools[/URL][/size][/font][/color][/B]>cpuid.exe -v | grep -iE "encls|enclv|cldemote|ptwrite|tpause|umonitor|umwait|movdir64b|movdiri|sha1msg1|rdpid|invpcid|rdpkru|wrpkru"
 EBX 10 Yes INVPCID instruction
 ECX  5 No  WAITPKG (UMWAIT instruction)
 ECX 22 No  RDPID (Read Processor ID) instruction
 ECX 25 No  CLDEMOTE (Cache Line Demote) instruction
 ECX 28 No  MOVDIR64B (Direct Store) instructions
on this i3 7020u @ 2.3
User avatar
evaluator
Posts: 1539
Joined: Tue Sep 18, 2001 2:00 pm

Post by evaluator »

this SYSTOOLS>cpuid.exe looks fun but.. are you sure it knows encls,wrpkru etc?? did simple string search & not found in :)
just dump CPUID.EAX=1 & CPUID.EAX=7,ECX=0
& and it is interesting about newer 9th & 10th gen Cores
User avatar
evaluator
Posts: 1539
Joined: Tue Sep 18, 2001 2:00 pm

CPUIDflags progy

Post by evaluator »

created little CPUIDflags progy :)
so much strings sorted in this thread, so I made from them progy. test it & upgrade. write if more interesting bits can be displayed.
added XGETBV ECX=1 case availability detection
attach in first post.
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