Hi! I've been seeking in vain for detailed information about AMD processors' supplementary debug facilities that are controlled by (undocumented, password protected!) MSR # C001_1024 "DbgCTLMSR2" and subsequent "DR0_Data_Match", "DR0_Data_Mask" & DR0_Addr_Mask (are there more of those ?)
Tantalisingly the register names which were leaked hint at how useful as a productivity tool the undocumented functions may be to programmers and reversers; unfortunately little more is available (the password itself is easily found by exhaustive search once the register numbers are known...). I've been trying to put those registers to work as a soothing since my dearest one passed away,but there is little hope of successwithout knowing at least the functions of the bits in the Control register (the low 8 bits are settable on my X32 Sempron 2400+ The registers /do/ affect DR0-based debugging,unfortunately I have not obtained more than the occasional crash or hang)... The data_match and Data_mask have full 32-bit width, while Address_match has the low 12-bits only settable (wild guess, an offset within "page" ?).
I find it unconceivable that such features be kept secret - especially so many years after they were introduced ! Doesn't someone in this select circle have access to the information, either from professional activity or personal reversing ?
It would be nice to have it published here either in the forum or the wiki.
Therefore we have set ourselves to solve this enigma and disclose our findings for the benefit of the community... Please keep visiting this forum thread and the results pages at my blog or the Collaborative RCE knowledge library
Best...
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